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» A Self-Reconfigurable Gate Array Architecture
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ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
14 years 4 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
CDES
2006
99views Hardware» more  CDES 2006»
13 years 9 months ago
Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates
Multi-valued Fredkin gates (MVFG) are reversible gates and they can be considered as modified version of the better known reversible gate the Fredkin gate. Reversible logic gates ...
Amin Ahsan Ali, Hafiz Md. Hasan Babu, Ahsan Raja C...
ISCAS
2003
IEEE
112views Hardware» more  ISCAS 2003»
14 years 27 days ago
Architectures for function evaluation on FPGAs
This paper presents a new family of architectures for multi-cycle area-efficient evaluation of elementary and composite functions, and an exploration of the design tradeoffs for i...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
FPL
2006
Springer
132views Hardware» more  FPL 2006»
13 years 11 months ago
Adaptive FPGAs: High-Level Architecture and a Synthesis Method
This paper presents preliminary work exploring adaptive field programmable gate arrays (AFPGAs). An AFPGA is adaptative in the sense that the functionality of subcircuits placed o...
Valavan Manohararajah, Stephen Dean Brown, Zvonko ...
TVLSI
2008
106views more  TVLSI 2008»
13 years 7 months ago
New Non-Volatile Memory Structures for FPGA Architectures
A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is describ...
David Choi, Kyu Choi, John D. Villasenor