In this paper we present a detailed analysis of the performance of the Decision Theoretic Read Delay (DTRD) optimistic synchronisation algorithm for simulations of Multistems. We ...
Michael Lees, Brian Logan, Dan Chen, Ton Oguara, G...
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...
This article presents a new evolutionary algorithm (EA) for induction of mixed decision trees. In nonterminal nodes of a mixed tree, different types of tests can be placed, rangin...
We use affine arithmetic to improve both the performance and the robustness of genetic programming for symbolic regression. During evolution, we use affine arithmetic to analyze e...
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, K...