Evaluating Fault Emulation on FPGA

Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. In order to evaluate possible simulation speed possibilities, we made a feasibility study of using reconfigurable hardware by emulating circuit under analysis together with fault insertion structures on FPGA. Experiments showed that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g., sequential circuits and/or genetic algorithms.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe
• Keywords: Fault Insertion Structures, Fault Simulation, FPL 2004, Test Pattern Generation