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» A Single-Path Chip-Multiprocessor System
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HPCA
2011
IEEE
12 years 11 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...
ISCA
2012
IEEE
274views Hardware» more  ISCA 2012»
11 years 10 months ago
The dynamic granularity memory system
Chip multiprocessors enable continued performance scaling with increasingly many cores per chip. As the throughput of computation outpaces available memory bandwidth, however, the...
Doe Hyun Yoon, Min Kyu Jeong, Michael Sullivan, Ma...
VTC
2008
IEEE
155views Communications» more  VTC 2008»
14 years 1 months ago
System Performance Analysis of Single-Path and Cooperative MIMO Relaying
— The demand for even higher data rates in future mobile communications systems calls for new techniques capable of improving the performance of cellular systems. One possibility...
Peter Rost, Fredrik Boye, Gerhard Fettweis
WORDS
2005
IEEE
14 years 1 months ago
Experiments with WCET-Oriented Programming and the Single-Path Architecture
The single-path software/hardware architecture has been conceived with the goal to support real-time task execution with highly predictable timing. By using WCET-oriented programm...
Peter P. Puschner
HPCA
2007
IEEE
14 years 7 months ago
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...
Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlk...