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» A Single-Path Chip-Multiprocessor System
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IJPP
2006
82views more  IJPP 2006»
13 years 7 months ago
Supporting Microthread Scheduling and Synchronisation in CMPs
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems. Usin...
Ian Bell, Nabil Hasasneh, Chris R. Jesshope
ICS
1999
Tsinghua U.
13 years 11 months ago
Improving the performance of speculatively parallel applications on the Hydra CMP
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
Kunle Olukotun, Lance Hammond, Mark Willey
ISCA
2008
IEEE
114views Hardware» more  ISCA 2008»
14 years 1 months ago
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...
Jae W. Lee, Man Cheuk Ng, Krste Asanovic
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
14 years 1 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 1 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...