420 search results - page 38 / 84 » A Small Test Generator for Large Designs |
WACV
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper we present a system for multi-pose face detection. Our system presents three main contributions. First, we introduce the use of asymmetric Haar features. Asymmetric ...
ET
2010
13 years 6 months ago
2010
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
ITC
1997
IEEE
13 years 12 months ago
1997
IEEE
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...
ITC
1994
IEEE
13 years 11 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— We present a general method to evaluate RF BuiltIn Self-Test (BIST) techniques during the design stage. In particular, the adaptive kernel estimator is used to construc...