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» A Spatial Logic for Concurrency
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ITC
1999
IEEE
105views Hardware» more  ITC 1999»
13 years 11 months ago
Finite state machine synthesis with concurrent error detection
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...
TPPP
1994
13 years 11 months ago
Time and Information in Sequential and Concurrent Computation
Time can be understood as dual to information in extant models of both sequential and concurrent computation. The basis for this duality is phase space, coordinatized by time and ...
Vaughan R. Pratt
FTCS
1994
140views more  FTCS 1994»
13 years 8 months ago
Concurrent Error Detection in Self-Timed VLSI
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are...
David A. Rennels, Hyeongil Kim
AICOM
2010
127views more  AICOM 2010»
13 years 7 months ago
Interactive verification of concurrent systems using symbolic execution
This paper presents an interactive proof method for the verification of temporal properties of concurrent systems based on symbolic execution. Symbolic execution is a well known a...
Simon Bäumler, Michael Balser, Florian Nafz, ...
ECBS
2009
IEEE
130views Hardware» more  ECBS 2009»
14 years 2 months ago
Validating and Dynamically Adapting and Composing Features in Concurrent Product-Lines Applications
With the pressing in-time-market towards customized services, software product lines (SPL) are increasingly characterizing most of software landscape. SPL are mainly structured th...
Nasreddine Aoumeur, Kamel Barkaoui, Gunter Saake