A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...
Time can be understood as dual to information in extant models of both sequential and concurrent computation. The basis for this duality is phase space, coordinatized by time and ...
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are...
This paper presents an interactive proof method for the verification of temporal properties of concurrent systems based on symbolic execution. Symbolic execution is a well known a...
With the pressing in-time-market towards customized services, software product lines (SPL) are increasingly characterizing most of software landscape. SPL are mainly structured th...