Concurrent Error Detection in Self-Timed VLSI

This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are compared with a checker that is composed of a tree of dual-rail (morphic) comparators to detect errors and signal completion. An efficient implementation is shown that compares favorably in speed and area with conventional completion signal generators. A simple pipeline is examined with error checkers at each computation stage and handshaking control circuits that are modified to improve error detection. Its error-detecting properties are discussed, and preliminary error simulation results are presented. Based on these studies we have concluded that self-timed logic offers considerable fault-tolerance potential due to its built-in redundancy that can be effectively exploited for error checking.

• Type: Conference
• Year: 1994
• Where: FTCS
• Authors: David A. Rennels, Hyeongil Kim
• Keywords: Concurrent Error Detection, Error Detection, FTCS 1994, Self-timed Vlsi Pipelines