Finite state machine synthesis with concurrent error detection

A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are checked independently. By checking parity on the present state instead of the next state, this technique allows detection of errors in bistable elements (that were hitherto not detected by many previous techniques) while requiring no changes in the original machine specifications. This paper also examines design choices with respect to parity prediction circuits. Two such examined choices are the multi-parity-group and the single-paritygroup techniques. A new state encoding technique based on the JEDI program is developed for the synthesis of the next-state logic with an additional parity output. Synthesis results produced by our proposed procedure for the MCNC'89 FSM benchmark circuits show on average a 25% reduction in literal counts compared to previous techniques.

• Type: Conference
• Year: 1999
• Where: ITC
• Authors: Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey
• Keywords: Finite State Machines, Hardware, ITC 1999, On-line Parity Checking, Parity Prediction Circuits