Sciweavers

340 search results - page 62 / 68
» A Statistical Performance Simulation Methodology for VLSI Ci...
Sort
View
ICCAD
2004
IEEE
128views Hardware» more  ICCAD 2004»
14 years 6 months ago
Power estimation for cycle-accurate functional descriptions of hardware
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj...
VLSID
2007
IEEE
85views VLSI» more  VLSID 2007»
14 years 10 months ago
Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective
In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo s...
Elias Kougianos, Saraju P. Mohanty
TON
1998
80views more  TON 1998»
13 years 9 months ago
Blocking and nonblocking multirate Clos switching networks
— This paper investigates in detail the blocking and nonblocking behavior of multirate Clos switching networks at the connection/virtual connection level. The results are applica...
Soung C. Liew, Ming-Hung Ng, Cathy W. Chan
TVLSI
2008
176views more  TVLSI 2008»
13 years 9 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
DAC
2005
ACM
14 years 10 months ago
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...