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ICCAD
2010
IEEE
158views Hardware» more  ICCAD 2010»
13 years 5 months ago
Novel binary linear programming for high performance clock mesh synthesis
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Minsik Cho, David Z. Pan, Ruchir Puri
CISS
2007
IEEE
13 years 7 months ago
Robust Routing in Wireless Multi-Hop Networks
This paper introduces a robust approach to stochastic multi-hop routing for wireless networks when the quality of links is modelled through a reliability matrix R. Yielding to the ...
Yuchen Wu, Alejandro Ribeiro, Georgios B. Giannaki...
LCTRTS
2010
Springer
13 years 5 months ago
Improving both the performance benefits and speed of optimization phase sequence searches
The issues of compiler optimization phase ordering and selection present important challenges to compiler developers in several domains, and in particular to the speed, code size,...
Prasad A. Kulkarni, Michael R. Jantz, David B. Wha...
LPNMR
2009
Springer
14 years 2 months ago
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
INFOCOM
2008
IEEE
14 years 2 months ago
A Distributed Optimization Algorithm for Multi-Hop Cognitive Radio Networks
Cognitive radio (CR) is a revolution in radio technology and is viewed as an enabling technology for dynamic spectrum access. This paper investigates how to design distributed alg...
Yi Shi, Y. Thomas Hou