131 search results - page 22 / 27 » A Structured Hardware Software Architecture for Embedded Sen... |
CODES
2008
IEEE
14 years 3 months ago
2008
IEEE
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
CODES
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
CLUSTER
2008
IEEE
14 years 3 months ago
2008
IEEE
—The industry is now in agreement that the future of architecture design lies in multiple cores. As a consequence, all computer systems today, from embedded devices to petascale ...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...
SIGCOMM
2009
ACM
14 years 3 months ago
2009
ACM
This paper presents BCube, a new network architecture specifically designed for shipping-container based, modular data centers. At the core of the BCube architecture is its serve...