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» A Study on Impact of Leakage Current on Dynamic Power
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CODES
2010
IEEE
13 years 5 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu
DT
2006
109views more  DT 2006»
13 years 7 months ago
Test Consideration for Nanometer-Scale CMOS Circuits
The ITRS (International Technology Roadmap for Semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing de...
Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
ISLPED
2006
ACM
117views Hardware» more  ISLPED 2006»
14 years 1 months ago
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
Samuel Rodríguez, Bruce L. Jacob
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
ICC
2007
IEEE
178views Communications» more  ICC 2007»
14 years 1 months ago
Impact of Transmission Power on the Performance of UDP in Vehicular Ad Hoc Networks
—With the availability of cheap and robust wireless devices there is demand for new applications in Vehicular Ad-hoc Networks (VANET). The challenge in implementing applications ...
Behrooz Khorashadi, Andrew Chen, Dipak Ghosal, Che...