284 search results - page 16 / 57 » A Synthesis Algorithm for Modular Design of Pipelined Circui... |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
FPGA
2007
ACM
14 years 2 months ago
2007
ACM
The application-specific multiprocessor System-on-a-Chip is a promising design alternative because of its high degree of flexibility, short development time, and potentially high ...
ISMVL
2008
IEEE
14 years 2 months ago
2008
IEEE
Compact realizations of reversible logic functions are of interest in the design of quantum computers. In this paper we present an exact synthesis algorithm, based on Boolean Sati...
DAC
2004
ACM
14 years 1 months ago
2004
ACM
Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tabl...
GLVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...