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ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
14 years 4 months ago
Robust analog/RF circuit design with projection-based posynomial modeling
In this paper we propose a RObust Analog Design tool (ROAD) for post-tuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthe...
Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence ...
ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
14 years 1 months ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
ANCS
2006
ACM
14 years 1 months ago
A practical fast parallel routing architecture for Clos networks
Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos network...
Si-Qing Zheng, Ashwin Gumaste, Enyue Lu
FPGA
2004
ACM
145views FPGA» more  FPGA 2004»
14 years 1 months ago
Exploration of pipelined FPGA interconnect structures
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
Akshay Sharma, Katherine Compton, Carl Ebeling, Sc...
ISCAS
2008
IEEE
160views Hardware» more  ISCAS 2008»
14 years 2 months ago
ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework
— This paper presents ATLAS - a framework for automated analog circuit synthesis that comprises of both topology generation and subsequent circuit sizing. A hierarchically arrang...
Angan Das, Ranga Vemuri