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ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
13 years 5 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 5 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
VLSI
2007
Springer
14 years 1 months ago
Incremental placement for structured ASICs using the transportation problem
— While physically driven synthesis techniques have proven to be an effective method to meet tight timing constraints required by a design, the incremental placement step during ...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
DAC
2005
ACM
13 years 9 months ago
Mixed signal design space exploration through analog platforms
We propose a hierarchical mixed signal design methodology based on the principles of Platform-Based Design (PBD). The methodology is a meet-in-the-middle approach where design com...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
DAC
2003
ACM
14 years 8 months ago
Distributed sleep transistor network for power reduction
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
Changbo Long, Lei He