284 search results - page 46 / 57 » A Synthesis Algorithm for Modular Design of Pipelined Circui... |
CGF
2011
12 years 11 months ago
2011
In this paper, we present a rapid prototyping framework for GPU-based volume rendering. Therefore, we propose a dynamic shader pipeline based on the SuperShader concept and illust...
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
Traditional metrics used to compare hardware designs include area, performance, and power. However, these metrics do not form a complete evaluation of reconfigurable hardware. For...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...