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DAC
2003
ACM
14 years 8 months ago
A transformation based algorithm for reversible logic synthesis
A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing...
D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
14 years 1 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 11 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
DAC
2004
ACM
14 years 8 months ago
A new heuristic algorithm for reversible logic synthesis
Reversible logic has applications in many fields, including quantum computing. Synthesis techniques for reversible circuits are not well developed, even for functions with a small...
Pawel Kerntopf
ASYNC
2003
IEEE
119views Hardware» more  ASYNC 2003»
14 years 1 months ago
Asynchronous DRAM Design and Synthesis
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
Virantha N. Ekanayake, Rajit Manohar