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» A System for Synthesizing Optimized FPGA Hardware from MATLA...
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FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 1 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
DAC
2003
ACM
14 years 8 months ago
Dynamic hardware/software partitioning: a first approach
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy co...
Greg Stitt, Roman L. Lysecky, Frank Vahid
ISCA
1990
IEEE
68views Hardware» more  ISCA 1990»
13 years 11 months ago
Maximizing Performance in a Striped Disk Array
Improvements in disk speeds have not kept up with improvements in processor and memory speeds. One way to correct the resulting speed mismatch is to stripe data across many disks. ...
Peter M. Chen, David A. Patterson
ATVA
2009
Springer
100views Hardware» more  ATVA 2009»
14 years 2 months ago
Dynamic Observers for the Synthesis of Opaque Systems
: In this paper, we address the problem of synthesizing opaque systems. A secret predicate S over the runs of a system G is opaque to an external user having partial observability ...
Franck Cassez, Jérémy Dubreil, Herv&...
ASPDAC
2008
ACM
101views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Interconnect modeling for improved system-level design optimization
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...
Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Ale...