209 search results - page 10 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper,...
ISCC
2005
IEEE
14 years 1 months ago
2005
IEEE
—A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optim...
MTDT
2003
IEEE
14 years 1 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
ISPD
2005
ACM
14 years 1 months ago
2005
ACM
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...
EVOW
2001
Springer
14 years 6 days ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...