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» A Systematic Approach for Designing Testable VLSI Circuits
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ICCD
2007
IEEE
161views Hardware» more  ICCD 2007»
14 years 4 months ago
Scan chain design for three-dimensional integrated circuits (3D ICs)
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...
Xiaoxia Wu, Paul Falkenstern, Yuan Xie
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
14 years 4 days ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
NIPS
2003
13 years 9 months ago
A Low-Power Analog VLSI Visual Collision Detector
We have designed and tested a single-chip analog VLSI sensor that detects imminent collisions by measuring radially expansive optic flow. The design of the chip is based on a mode...
Reid R. Harrison
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
14 years 8 months ago
Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing
Abstract--A novel input and output biasing circuit to extend the input common mode (CM) voltage range and the output swing to rail-to-rail in a low voltage op-amp in standard CMOS ...
S. V. Gopalaiah, A. P. Shivaprasad, Sukanta K. Pan...
VLSI
2007
Springer
14 years 1 months ago
Estimating design time for system circuits
System design complexity is growing rapidly. As a result, current development costs are constantly increasing. It is becoming increasingly difficult to estimate how much time it ...
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian G...