209 search results - page 37 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
DFT
2005
IEEE
14 years 1 months ago
2005
IEEE
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
DAC
2007
ACM
13 years 11 months ago
2007
ACM
This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed f...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...