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» A Systematic Approach for Designing Testable VLSI Circuits
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GLVLSI
2003
IEEE
186views VLSI» more  GLVLSI 2003»
15 years 11 months ago
A fast simulation approach for inductive effects of VLSI interconnects
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...
Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-D...
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
15 years 10 months ago
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
Norbert Fröhlich, Volker Gloeckel, Josef Flei...
GLVLSI
2003
IEEE
167views VLSI» more  GLVLSI 2003»
15 years 11 months ago
New approach to CMOS current reference with very low temperature coefficient
A novel CMOS current reference circuit with very low temperature coefficient is realized, by compensating the temperature performance of the resistor. This circuit gives out a cur...
Jiwei Chen, Bingxue Shi
VLSID
1996
IEEE
153views VLSI» more  VLSID 1996»
15 years 10 months ago
Design of high performance two stage CMOS cascode op-amps with stable biasing
The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various...
Pradip Mandal, V. Visvanathan
DAC
2005
ACM
15 years 7 months ago
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
Chong Zhao, Yi Zhao, Sujit Dey