Sciweavers

106 search results - page 12 / 22
» A Task-Centric Memory Model for Scalable Accelerator Archite...
Sort
View
ICC
2011
IEEE
269views Communications» more  ICC 2011»
12 years 7 months ago
Experimental Evaluation of Memory Management in Content-Centric Networking
Abstract—Content-Centric Networking is a new communication architecture that rethinks the Internet communication model, designed for point-to-point connections between hosts, and...
Giovanna Carofiglio, Vinicius Gehlen, Diego Perino
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
14 years 2 months ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
SIGMETRICS
2008
ACM
140views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
Scalable VPN routing via relaying
Enterprise customers are increasingly adopting MPLS (Multiprotocol Label Switching) VPN (Virtual Private Network) service that offers direct any-to-any reachability among the cust...
Changhoon Kim, Alexandre Gerber, Carsten Lund, Dan...
3DIC
2009
IEEE
146views Hardware» more  3DIC 2009»
14 years 2 months ago
A routerless system level interconnection network for 3D integrated systems
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
Kelli Ireland, Donald M. Chiarulli, Steven P. Levi...
EUROPAR
1997
Springer
14 years 1 days ago
Prefetching and Multithreading Performance in Bus-Based Multiprocessors with Petri Nets
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to ...
Edward D. Moreno, Sergio Takeo Kofuji, Marcelo H. ...