106 search results - page 5 / 22 » A Task-Centric Memory Model for Scalable Accelerator Archite... |
APPINF
2003
13 years 8 months ago
2003
Evolution of existing large telecommunications software currently became an important issue. Efficient methods are needed to componentize existing software identify existing compo...
MICRO
2010
IEEE
13 years 4 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
VLSISP
2008
13 years 6 months ago
2008
This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological op...
CLUSTER
2009
IEEE
13 years 4 months ago
2009
IEEE
With the advent of high-performance COTS clusters, there is a need for a simple, scalable and faulttolerant parallel programming and execution paradigm. In this paper, we show that...
CORR
2006
Springer
13 years 7 months ago
2006
Springer
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...