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DSN
2007
IEEE
14 years 2 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
VR
2002
IEEE
132views Virtual Reality» more  VR 2002»
14 years 25 days ago
Pop Through Button Devices for VE Navigation and Interaction
We present a novel class of virtual reality input devices that combine pop through buttons with 6 DOF trackers. Compared to similar devices that use conventional buttons, pop thro...
Robert C. Zeleznik, Joseph J. LaViola Jr., Daniel ...
ITC
2003
IEEE
205views Hardware» more  ITC 2003»
14 years 1 months ago
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...
MASCOTS
1997
13 years 9 months ago
A Hybrid Simulation Approach Enabling Performance Characterization of Large Software Systems
We describe a method for performance analysis of large software systems that combines a fast instruction-set simulator with off-line detailed analysis of segments of the execution...
Bengt Werner, Peter S. Magnusson
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
13 years 5 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen