899 search results - page 7 / 180 » A Temporal Language for SystemC |
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
—Today verification, testing and debugging of SystemC models can be applied at an early stage in the design process. To support these techniques gaining required information of ...
ERSA
2006
13 years 8 months ago
2006
Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the fun...
FDL
2006
IEEE
14 years 23 days ago
2006
IEEE
We present an introspection/reflection framework for SystemC which extracts design-relevant structure information and transaction data under any LRM-2.1 compliant simulation kern...
FDL
2003
IEEE
14 years 4 hour ago
2003
IEEE
With System on Chip low power constraints becoming increasingly important, emphasis is moving to architectural level, optimum memory organisation and system run time management. T...
WORDS
2005
IEEE
14 years 8 days ago
2005
IEEE
Reliable program Worst-Case Execution Time (WCET) estimates are a key component when designing and verifying real-time systems. One way to derive such estimates is by static WCET ...