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DAC
2006
ACM
16 years 3 months ago
Timing driven power gating
Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all ...
De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang,...
DAC
2006
ACM
16 years 3 months ago
Architecture-aware FPGA placement using metric embedding
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
Padmini Gopalakrishnan, Xin Li, Lawrence T. Pilegg...
DAC
2006
ACM
16 years 3 months ago
Fast analysis of structured power grid by triangularization based structure preserving model order reduction
In this paper, a Triangularization Based Structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is...
Hao Yu, Yiyu Shi, Lei He
DAC
2006
ACM
16 years 3 months ago
Placement of digital microfluidic biochips using the t-tree formulation
Droplet-based microfluidic biochips have recently gained much attention and are expected to revolutionize the biological laboratory procedure. As biochips are adopted for the comp...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
118
Voted
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 2 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...