264 search results - page 10 / 53 » A Time Predictable Instruction Cache for a Java Processor |
ISCA
1995
IEEE
14 years 7 days ago
1995
IEEE
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
TC
2002
13 years 8 months ago
2002
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction and speculatively executes its data-dependent instructions based on th...
ISCA
2000
IEEE
14 years 1 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
ISPASS
2009
IEEE
14 years 3 months ago
2009
IEEE
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...
RTSS
1994
IEEE
14 years 24 days ago
1994
IEEE
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently...