Understanding the backward slices of performance degrading instructions

For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static instructions, whose behavior cannot be anticipated using current branch predictors and caches, contribute a large fraction of such performance degrading events. This paper analyzes the dynamic instruction stream leading up to these performance degrading instructions to identify the operations necessary to execute them early. The backward slice (the subset of the program that relates to the instruction) of these performance degrading instructions, if small compared to the whole dynamic instruction stream, can be pre-executed to hide the instruction’s latency. To overcome conservative dependence assumptions that result in large slices, speculation can be used, resulting in speculative slices. This paper provides an initial characterization of the backward slices of L2 data cache misses and branch misprediction...

• Type: Conference
• Year: 2000
• Where: ISCA
• Authors: Craig B. Zilles, Gurindar S. Sohi
• Keywords: Cache Misses, Dynamic Instruction Stream, Hardware, ISCA 2000, Performance Degrading Instruction