264 search results - page 15 / 53 » A Time Predictable Instruction Cache for a Java Processor |
ISCA
1997
IEEE
14 years 27 days ago
1997
IEEE
Prefetching is one approach to reducing the latency of memory operations in modern computer systems. In this paper, we describe the Markov prefetcher. This prefetcher acts as an i...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
MICRO
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...
CONCURRENCY
2006
13 years 8 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
RTSS
2006
IEEE
14 years 2 months ago
2006
IEEE
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...