Current instruction fetch policies in SMT processors are oriented towards optimization of overall throughput and/or fairness. However, they provide no control over how individual ...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
Multicores are becoming ubiquitous, not only in general-purpose but also embedded computing. This trend is a reflexion of contemporary embedded applications posing steadily incre...
Abhik Sarkar, Frank Mueller, Harini Ramaprasad, Si...
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio...
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is...