264 search results - page 30 / 53 » A Time Predictable Instruction Cache for a Java Processor |
RTAS
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper investigates how dynamic branch prediction in a microprocessor affects the predictability of execution time for software running on that processor. By means of experim...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
RTSS
1999
IEEE
14 years 28 days ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
IEEEPACT
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be e...
HIPC
1999
Springer
14 years 27 days ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...