264 search results - page 34 / 53 » A Time Predictable Instruction Cache for a Java Processor |
ISCA
2000
IEEE
14 years 6 days ago
2000
IEEE
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
FSE
2006
Springer
14 years 9 days ago
2006
Springer
This paper studies the state-of-the-art software optimization methodology for symmetric cryptographic primitives on the new 64-bit x64 processors, AMD Athlon64 (AMD64) and Intel Pe...
LCPC
2005
Springer
14 years 2 months ago
2005
Springer
Programming network processors remains a challenging task since their birth until recently when high-level programming environments for them are emerging. By employing domain speci...
MICRO
1998
IEEE
14 years 26 days ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
ISCA
1995
IEEE
14 years 5 days ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...