Reconfigurable caches and their application to media processing

High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing. It is therefore important to ensure that architectural features that use a signi cant fraction of the on-chip transistors are applicable across these di erent domains. For example, current processor designs often devote the largest fraction of on-chip transistors up to 80 to caches. Many workloads, however, do not make e ective use of large caches; e.g., media processing workloads which often have streaming data access patterns and large working sets. This paper proposes a new recon gurable cache design. This design enables the cache SRAM arrays to be dynamically divided into multiple partitions that can be used for di erent processor activities. These activities can bene t applications that would otherwise not use the storage allocated to large conventional caches. Our design involves relatively few modi c...

• Type: Conference
• Year: 2000
• Where: ISCA
• Authors: Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi
• Keywords: Hardware, ISCA 2000, Media Processing, On-chip Transistors, Recon Gurable Caches