264 search results - page 47 / 53 » A Time Predictable Instruction Cache for a Java Processor |
RTAS
2006
IEEE
14 years 2 months ago
2006
IEEE
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power pr...
SIGCOMM
1997
ACM
14 years 23 days ago
1997
ACM
For some time, the networking communityhas assumed that it is impossible to do IP routing lookups in software fast enough to support gigabit speeds. IP routing lookups must nd th...
ICS
2007
Tsinghua U.
14 years 2 months ago
2007
Tsinghua U.
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
MICRO
1999
IEEE
14 years 26 days ago
1999
IEEE
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...