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» A Time Predictable Instruction Cache for a Java Processor
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ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
14 years 13 days ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
14 years 1 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin
SAC
2008
ACM
13 years 8 months ago
Filtering drowsy instruction cache to achieve better efficiency
Leakage power in cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed ...
Roberto Giorgi, Paolo Bennati
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
14 years 7 days ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
CSREAESA
2003
13 years 10 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...