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ICS
2009
Tsinghua U.
13 years 6 months ago
Refereeing conflicts in hardware transactional memory
In the search for high performance, most transactional memory (TM) systems execute atomic blocks concurrently and must thus be prepared for data conflicts. The TM system must then...
Arrvindh Shriraman, Sandhya Dwarkadas
KBSE
2006
IEEE
14 years 3 months ago
ArchTrace: Policy-Based Support for Managing Evolving Architecture-to-Implementation Traceability Links
Traditional techniques of traceability detection and management are not equipped to handle evolution. This is a problem for the field of software architecture, where it is critica...
Leonardo Gresta Paulino Murta, André van de...
ICITA
2005
IEEE
14 years 2 months ago
p-MANET: Efficient Power Saving Protocol for Multi-Hop Mobile Ad Hoc Networks
In this paper, we propose an efficient power saving protocol for multi-hop mobile ad hoc networks, called p-MANET. Our design is expected as a new foundation MAC layer power savin...
Chiung-Ying Wang, Chi-Jen Wu, Guan-Nan Chen, Ren-H...
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
14 years 2 months ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong
DSD
2010
IEEE
153views Hardware» more  DSD 2010»
13 years 9 months ago
Simulation of High-Performance Memory Allocators
—Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern highperformance applications. To optimize metrics like performance, memory us...
José Luis Risco-Martín, José ...