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DAC
2005
ACM
14 years 21 days ago
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
In this paper, we analyze the effect of jitter in track and hold circuits. The output spectrum is obtained in terms of the system function of the track and hold. It is a fairly g...
V. Vasudevan
VLDB
2007
ACM
198views Database» more  VLDB 2007»
14 years 11 months ago
The End of an Architectural Era (It's Time for a Complete Rewrite)
In previous papers [SC05, SBC+07], some of us predicted the end of "one size fits all" as a commercial relational DBMS paradigm. These papers presented reasons and exper...
Michael Stonebraker, Samuel Madden, Daniel J. Abad...
ISCA
2010
IEEE
181views Hardware» more  ISCA 2010»
14 years 3 months ago
ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violations
In this paper, we propose ColorSafe, an architecture that detects and dynamically avoids single- and multi-variable atomicity violation bugs. The key idea is to group related data...
Brandon Lucia, Luis Ceze, Karin Strauss
CIKM
1999
Springer
14 years 3 months ago
Architecture of a Networked Image Search and Retrieval System
Large scale networked image retrieval systems face a number of problems that are not fully satis ed by current systems. On one hand, integrated solutions that store all image data...
Roger Weber, Jürg Bolliger, Thomas R. Gross, ...
DAC
2005
ACM
14 years 11 months ago
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
Kenneth Eguro, Scott Hauck, Akshay Sharma