Sciweavers

3955 search results - page 6 / 791
» A Transactional Architecture for Simulation
Sort
View
CODES
2004
IEEE
13 years 11 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
MICRO
2010
IEEE
242views Hardware» more  MICRO 2010»
13 years 5 months ago
ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically exec...
Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, M...
SPAA
2010
ACM
14 years 22 days ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo...
SBACPAD
2004
IEEE
144views Hardware» more  SBACPAD 2004»
13 years 9 months ago
Improving Server Performance on Transaction Processing Workloads by Enhanced Data Placement
Modern servers access large volumes of data while running commercial workloads. The data is typically spread among several storage devices (e.g. disks). Carefully placing the data...
Juan Rubio, Charles Lefurgy, Lizy Kurian John
POS
1998
Springer
14 years 4 days ago
The Transactional Object Cache: A Foundation for High Performance Persistent System Construction
This paper argues that caching, atomicity and layering are fundamental to persistent systems, and that the transactional object cache architecture, as an embodiment of these conce...
Stephen Blackburn, Robin Stanton