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» A Transactional Architecture for Simulation
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GLVLSI
2000
IEEE
92views VLSI» more  GLVLSI 2000»
14 years 1 months ago
SPARTA: Simulation of Physics on a Real-Time Architecture
Abstract - In this paper, we discuss hardware acceleration for real-time physical modeling that would allow for realistic virtual environments. Additionally, we propose algorithms ...
Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irw...
DATE
1999
IEEE
115views Hardware» more  DATE 1999»
14 years 1 months ago
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability
We describe EXPRESSION, a language supporting architectural design space exploration for embedded Systems-onChip (SOC) and automatic generation of a retargetable compiler/simulato...
Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh K...
LCTRTS
2004
Springer
14 years 2 months ago
Spinach: a liberty-based simulator for programmable network interface architectures
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
Paul Willmann, Michael Brogioli, Vijay S. Pai
E4MAS
2005
Springer
14 years 2 months ago
An Architecture for MAS Simulation Environments
In this paper we discuss the model of an environment, acting as a first-class entity for MAS Simulation. To illustrate, we use the DIVAs framework’s design and implementation de...
Renee Steiner, Gary Leask, Rym Mili
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
14 years 3 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer