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» A Visual Approach to Validating System Level Designs
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ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
14 years 5 months ago
Quality Improvement Methods for System-Level Stimuli Generation
Functional verification of systems is aimed at validating the integration of previously verified components. It deals with complex designs, and invariably suffers from scarce re...
Roy Emek, Itai Jaeger, Yoav Katz, Yehuda Naveh
SAMOS
2007
Springer
14 years 3 months ago
An Evolutionary Approach to Area-Time Optimization of FPGA designs
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...
Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Paler...
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
14 years 1 months ago
System Level Design Using C++
This paper discusses the use of C++ for the design of digital systems. The paper distinguishes a number of different approaches towards the use of programming languages for digita...
Diederik Verkest, Joachim Kunkel, Frank Schirrmeis...
DATE
2003
IEEE
120views Hardware» more  DATE 2003»
14 years 2 months ago
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain
Embedded systems design requires the development of complex HW modules to cope with the most stringent timing constraints of the specifications. This implies the need to update an...
Massimo Bombana, Francesco Bruschi
CSMR
2008
IEEE
14 years 3 months ago
Visual Detection of Design Anomalies
Design anomalies, introduced during software evolution, are frequent causes of low maintainability and low flexibility to future changes. Because of the required knowledge, an im...
Karim Dhambri, Houari A. Sahraoui, Pierre Poulin