Sciweavers

2695 search results - page 3 / 539
» A Visual Approach to Validating System Level Designs
Sort
View
CAISE
2010
Springer
13 years 8 months ago
Design and Verification of Instantiable Compliance Rule Graphs in Process-Aware Information Systems
For enterprises it has become crucial to check compliance of their business processes with certain rules such as medical guidelines or financial regulations. When automating compli...
Linh Thao Ly, Stefanie Rinderle-Ma, Peter Dadam
ISSS
2002
IEEE
130views Hardware» more  ISSS 2002»
14 years 16 days ago
System-Level Modeling of a Network Switch SoC
We present the modeling of the high-level design of a next generation network switch from the perspective of a ComputerAided Design (CAD) team within the larger context of a desig...
Andrew S. Cassidy, Christopher P. Andrews, Donald ...
AVI
2004
13 years 9 months ago
Identification and validation of cognitive design principles for automated generation of assembly instructions
Designing effective instructions for everyday products is challenging. One reason is that designers lack a set of design principles for producing visually comprehensible and acces...
Julie Heiser, Doantam Phan, Maneesh Agrawala, Barb...
FDL
2004
IEEE
13 years 11 months ago
SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip
Reconfigurability is becoming an important part of System-on-Chip (SoC) design to cope with the increasing demands for simultaneous flexibility and computational power. Current ha...
Kari Tiensyrjä, Miroslav Cupák, Kostas...
FDL
2008
IEEE
13 years 9 months ago
Scenario-based Validation of Embedded Systems
This paper describes a scenario-based methodology em-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existi...
Angelo Gargantini, Elvinia Riccobene, Patrizia Sca...