228 search results - page 11 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
DAC
1997
ACM
14 years 4 days ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
TC
2008
13 years 8 months ago
2008
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
- The large magnitude of supply/ground bounces, which arise from power mode transitions in power gating structures, may cause spurious transitions in a circuit. This can result in ...
DAC
2001
ACM
14 years 9 months ago
2001
ACM
In this paper, we propose preconditioned Krylov-subspace iterative methods to perform efficient DC and transient simulations for large-scale linear circuits with an emphasis on po...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...