127 search results - page 14 / 26 » A cache-defect-aware code placement algorithm for improving ... |
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents an automated performance tuning solution, which partitions a program into a number of tuning sections and finds the best combination of compiler options for e...
SAC
2008
ACM
13 years 7 months ago
2008
ACM
To use multiple memory banks in parallel is a nature approach to boost the performance of flash-memory storage systems. However, realistic data-access localities unevenly load eac...
VTC
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper considers the problem of selecting a subset of nodes in a two-hop wireless network to act as relays in aiding the communication between the source-destination pair. Opt...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
INFORMATICALT
2006
13 years 7 months ago
2006
The paper describes the development and performance of parallel algorithms for the discrete element method (DEM) software. Spatial domain decomposition strategy and message passing...