127 search results - page 16 / 26 » A cache-defect-aware code placement algorithm for improving ... |
127
Voted
IPPS
1998
IEEE
15 years 7 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
132
Voted
CF
2005
ACM
15 years 4 months ago
2005
ACM
This paper evaluates how much extended dictionary-based code compression techniques can reduce the static code size. In their simplest form, such methods statically identify ident...
142
Voted
LCTRTS
2007
Springer
15 years 9 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
136
Voted
EMSOFT
2004
Springer
15 years 8 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
124
Voted
DAC
2008
ACM
15 years 4 months ago
2008
ACM
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...