Sciweavers

71 search results - page 11 / 15
» A case for a working-set-based memory hierarchy
Sort
View
CASES
2004
ACM
14 years 2 months ago
A post-compiler approach to scratchpad mapping of code
ScratchPad Memories (SPMs) are commonly used in embedded systems because they are more energy-efficient than caches and enable tighter application control on the memory hierarchy...
Federico Angiolini, Francesco Menichelli, Alberto ...
CASES
2008
ACM
13 years 10 months ago
SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip
fficient Programming Abstractions for Heterogeneous Multicore Systems on Chip Alastair D. Reid Krisztian Flautner Edmund Grimley-Evans ARM Ltd Yuan Lin University of Michigan The ...
Alastair D. Reid, Krisztián Flautner, Edmun...
TJS
2002
121views more  TJS 2002»
13 years 8 months ago
Precise Data Locality Optimization of Nested Loops
A significant source for enhancing application performance and for reducing power consumption in embedded processor applications is to improve the usage of the memory hierarchy. In...
Vincent Loechner, Benoît Meister, Philippe C...
EUROPAR
2010
Springer
13 years 9 months ago
Optimized Dense Matrix Multiplication on a Many-Core Architecture
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
Elkin Garcia, Ioannis E. Venetis, Rishi Khan, Guan...
PLDI
2005
ACM
14 years 2 months ago
Automatic pool allocation: improving performance by controlling data structure layout in the heap
This paper describes Automatic Pool Allocation, a transformation framework that segregates distinct instances of heap-based data structures into seperate memory pools and allows h...
Chris Lattner, Vikram S. Adve