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» A cell-based power estimation in CMOS combinational circuits
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ASPDAC
2007
ACM
136views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...
Georges G. E. Gielen
CACM
2000
158views more  CACM 2000»
13 years 7 months ago
Wireless Integrated Network Sensors
Wireless Integrated Network Sensors (WINS) now provide a new monitoring and control capability for transportation, manufacturing, health care, environmental monitoring, and safety...
Gregory J. Pottie, William J. Kaiser
FPGA
2006
ACM
93views FPGA» more  FPGA 2006»
13 years 11 months ago
Measuring the gap between FPGAs and ASICs
This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power cons...
Ian Kuon, Jonathan Rose
DAC
1997
ACM
13 years 11 months ago
Power Macromodeling for High Level Power Estimation
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input output signal switching activity. The resulting...
Subodh Gupta, Farid N. Najm
MJ
2008
111views more  MJ 2008»
13 years 7 months ago
CMOL: Second life for silicon
This report is a brief review of the recent work on architectures for the prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including digital memories, reco...
Konstantin K. Likharev