Sciweavers

1008 search results - page 165 / 202
» A cis-regulatory logic simulator
Sort
View
ISCC
2006
IEEE
129views Communications» more  ISCC 2006»
14 years 5 months ago
A Semantic Overlay Network for P2P Schema-Based Data Integration
Abstract— Today data sources are pervasive and their number is growing tremendously. Current tools are not prepared to exploit this unprecedented amount of information and to cop...
Carmela Comito, Simon Patarin, Domenico Talia
ISQED
2006
IEEE
155views Hardware» more  ISQED 2006»
14 years 5 months ago
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
Bin Zhang, Wei-Shen Wang, Michael Orshansky
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
14 years 4 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
ICPP
2005
IEEE
14 years 4 months ago
Locality-Aware Randomized Load Balancing Algorithms for DHT Networks
Structured P2P overlay networks based on a consistent hashing function have an aftermath load balance problem that needs to be dealt with. A load balancing method should take into...
Haiying Shen, Cheng-Zhong Xu
ISCAS
2005
IEEE
224views Hardware» more  ISCAS 2005»
14 years 4 months ago
A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the...
Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga