1008 search results - page 46 / 202 » A cis-regulatory logic simulator |
APCCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
PATMOS
2004
Springer
14 years 2 months ago
2004
Springer
Abstract. The logical effort method has appeared very convenient for fast estimation and optimization of single paths. However it necessitates a calibration of all the gates of the...
PDP
1997
IEEE
14 years 27 days ago
1997
IEEE
Event tracing and monitoring of parallel applications are difficult if each processor has its own unsynchronized clock. A survey is given on several strategies to generate a glob...
IJSYSC
2006
13 years 8 months ago
2006
: A backlash compensator is designed for nonlinear systems using the fuzzy logic. The classification property of fuzzy logic systems makes them a natural candidate for the rejectio...
CHES
2009
Springer
14 years 3 months ago
2009
Springer
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...