Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
Abstract. The logical effort method has appeared very convenient for fast estimation and optimization of single paths. However it necessitates a calibration of all the gates of the...
B. Lasbouygues, Robin Wilson, Philippe Maurine, Na...
Event tracing and monitoring of parallel applications are difficult if each processor has its own unsynchronized clock. A survey is given on several strategies to generate a glob...
: A backlash compensator is designed for nonlinear systems using the fuzzy logic. The classification property of fuzzy logic systems makes them a natural candidate for the rejectio...
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...
Francesco Regazzoni, Alessandro Cevrero, Fran&cced...